1. Field of the Invention
The present invention relates generally to a shift register circuit and a display unit incorporating the same, and more particularly, to an active matrix addressing mode liquid crystal display unit, in which a driver and a pixel portion connected thereto are integrated. The driver has a shift register circuit including a plurality of signal shifting systems.
2. Description of the Related Art
Recently, active matrix addressing mode liquid crystal display (LCD) units employing thin film transistors (TFT's) are known to provide a high image quality display. Dot matrix LCD's employing dots arranged in the form of a matrix are classified into two types: simple matrix addressing mode and active matrix addressing mode.
In the simple matrix addressing mode, the liquid crystal in the pixels arranged in the matrix is directly driven in synchronization with scanning signals. A liquid crystal panel of the LCD is formed by the use of electrodes and a liquid crystal. Accordingly, when the number of scanning lines is increased, the duty cycle for each pixel is shortened. This brings about contrast reduction.
In the active matrix addressing mode, each pixel arranged in the matrix has an active element as a pixel driving element and a signal storage element (i.e., pixel capacitance). Both the driving element and the storage element are integrated in the pixel. Each pixel performs signal storing behavior, and the liquid crystal is driven semi-statically. In other words, the pixel driving element functions as a switch element that is controlled in response to scanning signals. When the pixel driving element is actuated, the associated pixel receives a data signal indicating display data via the pixel driving element to drive the liquid crystal. When the pixel driving element is then deactivated, the data signal applied to the pixel is stored in the form of electric charge in the associated signal storage element. Driving of the liquid crystal is continuously controlled based on the electric charge thus stored until the pixel driving element resumes an ON-state. Accordingly, in spite of the fact that the driving time for each pixel is reduced due to the increased number of the scanning lines, driving control of the liquid crystal is not affected, and there is no contrast reduction. Therefore, the active matrix addressing mode provides a very high image quality display compared with the simple matrix addressing mode.
The active matrix addressing mode is classified depending on the type of the pixel driving elements into two types; three-terminal transistor type and diode type. Although the transistor type matrix addressing mode involves difficulties in production compared with the diode type matrix driving mode, the transistor type has superior contrast and resolution properties as compared to the diode type. Further, the transistor type matrix addressing mode permits attainment of CRT image quality in LCD units.
FIG. 1 shows a data driver incorporated in a conventional active matrix addressing mode LCD unit. This data driver includes a shift register circuit 50, which has four signal shifting systems. The shift register circuit 50 includes a plurality of shift register blocks (hereinafter simply called "register blocks") 51 to 53 and a plurality of connection circuits 60 arranged in a line with the register blocks. The individual connection circuits 60 are arranged with a predetermined number of register blocks in between, and each connection circuit 60 includes four connecting sections 61 to 64, which belong to the first to fourth systems.
Each of the register blocks 51 to 53 has four groups of shift registers 54 to 57, which belong to the first to fourth systems and are arranged in the order from the first system to the fourth system. Each of the shift register groups 54 to 57 of the first to fourth systems has a normal shift register and a redundant shift register. More specifically, the shift register groups 54 to 57 are arranged in the order of the normal and redundant shift registers SSR1 and RSR1 of the first system, the normal and redundant shift registers of the second system, the normal and redundant shift registers of the third system and the normal and redundant shift registers of the fourth system.
The individual normal shift registers SSR1 belonging to the first system of the individual register blocks 51 to 53 are connected in series. The individual redundant shift registers RSR1 belonging to the first system of the register blocks 51 to 53 are also connected in series. The individual normal shift registers belonging to the second, third and fourth systems of the register blocks 51 to 53 are likewise connected in series system by system. The individual redundant shift registers belonging to the second, third and fourth systems of the register blocks 51-53 are likewise connected in series system by system.
The first connecting section 61 of the connection circuit 60, arranged between the register blocks 51 and 52, connects the first-system shift register group 54 (the normal and redundant shift registers SSR1 and RSR1) of the register block 51 to the first-system shift register group 54 (the normal and redundant shift registers SSR1 and RSR1) of the register block 52. The second connecting section 62 connects the second-system shift register group 55 of the register block 51 to the second-system shift register group 55 of the register block 52. The third connecting section 63 connects the third-system shift register group 56 of the register block 51 to the third-system shift register group 56 of the register block 52. The fourth connecting section 64 connects the fourth-system shift register group 57 of the register block 51 to the fourth-system shift register group 57 of the register block 52.
Each of the connecting sections 61 to 64 determines if the normal shift register belonging to each system is performing the normal shift operation, and when the normal shift register does not execute the normal shift operation, each connecting section switches the shift operation to that of the redundant shift register and sends a data signal to the normal and redundant shift registers in the subsequent stage and to a sampling transistor circuit (not shown). The sampling transistor circuit performs an ON/OFF action in response to the data signal from the shift register circuit and samples a video signal supplied from a video signal processor (not shown). The sampled video signal is applied to the individual pixel cells to display an image on the screen of the LCD unit.
The interconnection distance between the register blocks 51 and 52, with the connecting sections 61 to 64 of the individual systems, arranged in the above-described manner, is longer than the interconnection distance between the register blocks 52 and 53 that have no connecting sections. That is, the data transmission time t1 from the output point of a data signal from the register block 51 to the reception point of the data signal by the register block 52 is longer than the data transmission time t2 from the output point of a data signal from the register block 52 to the reception point of the data signal by the register block 53. Therefore, the propagation delay time of a data signal between the register blocks 51 and 52 between which the connection circuit 60 is provided is longer than the propagation delay time of a data signal between the register blocks 52 and 53 between which no connection circuit is provided. Consequently, the LCD unit as a whole locally has those portions at which the propagation delay time of a data signal is longer, i.e., the propagation delay time varies from one place to another. This results in delayed sampling of a video signal by the enabled sampling transistor circuit, thus making it difficult to accurately display an image on the screen of a display unit. As a result, an image is discontinuously displayed on the screen, which is undesirable for a user. As a solution to this shortcoming, a video signal processor, timing controller or the like, which is provided separate from the LCD unit, may be used to reduce the video-signal sampling delay. In this case, however, the circuit structure of the display unit becomes complicated and the circuit scale becomes undesirably large.